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ds07-12601-1e fujitsu semiconductor data sheet 8-bit proprietary microcontrollers cmos f 2 mc-8fx mb95100a series MB95107A/f108as/f108aw/fv100a-101 description the mb95100a series is general-purpose, single-chip microc ontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. feature ? f 2 mc-8fx cpu core instruction set optimized for controllers ? multiplication and division instructions 16-bit arithmetic operations bit test branch instruction bit manipulation instructions etc. ? clock main clock main pll clock subclock (for dual clock product) sub pll clock (for dual clock product) (continued) packages 64-pin plastic lqfp 64-pin plastic lqfp (fpt-64p-m03) (fpt-64p-m09)
mb95100a series 2 (continued) ? timer 8/16-bit compound timer 2 channels 16-bit reload timer 8/16-bit ppg 2 channels 16-bit ppg 2 channels timebase timer watch prescaler (for dual clock product) ? lin-uart full duplex double buffer clock asynchronous or synchronous serial transfer capable ? uart/sio clock asynchronous or synchronous serial transfer capable ? i 2 c* built-in wake-up function ? external interrupt interrupt by edge detection (rising, falling, or both edges can be selected) can be used to recover from low-power consumption modes. ? 10-bit a/d converter 10-bit resolution ? low-power consumption (standby mode) stop mode sleep mode watch mode (for dual clock product) timebase timer mode ? i/o port: max 55 general-purpose i/o ports (nch open drain) : 6 ports general-purpose i/o ports (cmos) : 49 ports * : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these com- ponents in an i 2 c system provided that the system conforms to the i 2 c standard specificat ion as defined by philips.
mb95100a series 3 product lineup (continued) part number parameter MB95107A mb95f108as mb95f108aw mb95fv100a-101 type mask product flash product eva product rom capacity 48 kb 60 kb ram capacity 2 kb 3.75 kb reset output no option selectable single/dual -system* 2 single-system dual-system selectable single/dual -system* 1 cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, and 16 bits minimum instruction execution time : 0.1 s (at internal 10 mhz) interrupt processing time : 0.9 s (at internal 10 mhz) ports (max 55 ports) general-purpose i/o port (nch open drain) general-purpose i/o port (cmos) : 6 ports : 49 ports timebase timer interrupt cycle : 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 mhz) watchdog timer reset generated cycle at main oscillation clock 10 mhz : min 105 ms at sub oscillation clock 32.768 khz (for dual clock product) : min 250 ms wild register capable of replacing 3 bytes of data i 2 c bus master/slave sending and receiving bus error function an d arbitration function detecting transmitting direction function start condition repeated generat ion and detection functions built-in wake-up function uart/sio data transfer capable in uart/sio full duplex double buffer, variable data leng th (5/6/7/8-bit), built-in baud rate genera- tor transfer rate : 2400 bps to 1 25000 bps (at machine clock 10 mhz) nrz type transfer format, error detected function lsb-first or msb-first can be selected. clock synchronous (sio) or clock asyn chronous (uart) data transfer capable lin-uart dedicated reload timer allowing a wide r ange of communication speeds to be set. capable of data transfer synchronous or asynchronous to clock signal. lin functions available as the lin master or lin slave. a/d converter (12 channels) 8-bit or 10-bit resolution can be selected. 16-bit reload timer two clock modes and two counter operati ng modes can be selected. square wave- form output count clock : 7 internal clocks and external clock can be selected. peripheral functions
mb95100a series 4 (continued) *1 : change by the switch on mcu board. *2 : specify clock mode when ordering mask rom. part number parameter MB95107A mb95f108as mb95f108aw mb95fv100a-101 8/16-bit compound tim- er (2 channels) each channel of the timer can be used as ?8-bit timer 2 channels? or ?16-bit timer 1 channel?. built-in timer function, pwc function, pw m function, capture function and square waveform output count clock : 7 internal clocks and external clock can be selected. 16-bit ppg (2 channels) pwm mode or one-shot mode can be selected. counter operating clock : eight selectable clock sources support for external trigger start 8/16-bit ppg (2 channels) each channel of the ppg can be used as ? 8-bit ppg 2 channels ? or ? 16-bit ppg 1 channel ? . counter operating clock : eight selectable clock sources watch counter (for dual clock product) count clock : four selectable clock s ources (125 ms, 250 ms, 500 ms, or 1 s) counter value can be set from 0 to 63 . (capable of counting for 1 minute) watch prescaler (for dual clock product) four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) external interrupt (12 channels) interrupt by edge detection (rising, fa lling, or both edges can be selected.) can be used to recove r from standby modes. standby mode sleep, stop, watch, and timebase timer peripheral functions
mb95100a series 5 select of oscillation stabilization wait time (mask product only) for the mask product, you can set the mask option when ordering mask rom to select the initial value of main clock oscillation stabilization wait time from among the following four values. note that the eva and flash products are fixed their initia l value of main clock oscillation stabilization wait time at the maximum value. packages and corresponding products : available : unavailable oscillation stabilization wait time remarks (2 2 -2) /f ch 0.5 s (at main oscillation clock 4 mhz) (2 12 -2) /f ch approx. 1.02 ms (at main oscillation clock 4 mhz) (2 13 -2) /f ch approx. 2.05 ms (at main oscillation clock 4 mhz) (2 14 -2) /f ch approx. 4.10 ms (at main oscillation clock 4 mhz) part number package MB95107A mb95f108as mb95f108aw mb95fv100a-101 fpt-64p-m03 fpt-64p-m09 bga-224p-m08
mb95100a series 6 differences among products and notes on selecting products ? notes on using eva products the eva product has not only the func tions of the mb95100a corresponding products series but also those of other products to support software development for multiple series and models of the f 2 mc-8fx family. the i/ o addresses for peripheral resources not used by th e mb95100a series are th erefore access-barred. read/ write access to these access-barred addresses may c ause peripheral resources supposed to be unused to operate, resulting in unexpected malf unctions of hardware or software. take particular care not to use word, long word, or si milar access to read or write odd numbered bytes in the prohibited areas. note that the values read from barred addresses ar e different between the eva product and the flash or mask product. therefore, the data must not be used for software processing. the eva product do not support the functions of some bits in single-byte registers. read/write access to these bits does not cause hardware malfunctions. since the eva, flash, and mask products are designed to behave completely the same way in terms of hardware and software, you do not have to pay special attention to specific products. ? difference of memory spaces if the amount of memory on the eva product is differ ent from that of the flas h or mask product, carefully check the difference in the amount of memory from th e model to be actually used when developing software. ? current consumption the current consumption of flash product is typically greater than for mask rom product. for details of current consumption, refer to ? electrical characteristics?. ? package for details of information on each package, see ? package dimensions?. ? operating voltage the operating voltage are different am ong the eva, flash and mask products. for details of operating voltage, refer to ? electrical characteristics? ? difference between rst and mod pins the rst and mod pins are hysteresis inputs on the mask pr oduct. a pull - down resistor is provided for the mod pin of the mask product.
mb95100a series 7 pin assignment avss p30/an0 0 p31/an0 1 p32/an0 2 p33/an0 3 p34/an0 4 p35/an0 5 p36/an0 6 p37/an0 7 p40/an0 8 p41/an0 9 p42/an1 0 p43/an1 1 p67/sin p66/sot p65/sck 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avcc 148 p64/ec1 avr 247 p63/to11 p e3/int13 346 p62/to10 p e2/int12 445 p61/ppg11 p e1/int11 544 p60/ppg10 p e0/int10 643 p53/trg1 p83 742 p52/ppg1 p82 841 p51/sda0 p81 940 p50/scl0 p80 10 39 p24/ec0 p71/ti0 11 38 p23/to01 p70/to0 12 37 p22/to00 mod 13 36 p21/ppg01 x0 14 35 p20/ppg00 x1 15 34 p14/ppg0 vss 16 33 p13/trg0/adt g 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vcc pg0 pg2/x1a pg1/x0a rst p 00/int00 p 01/int01 p 02/int02 p 03/int03 p 04/int04 p 05/int05 p 06/int06 p 07/int07 p10/ui0 p11/uo0 p12uck0 64 top view
mb95100a series 8 pin description (continued) pin no. pin name circuit type description 1avcc ? a/d power supply pin 2avr ? a/d reference input pin 3pe3/int13 p general-purpose i/o port the pins are shared with the external interrupt input. 4pe2/int12 5pe1/int11 6pe0/int10 7p83 o general-purpose i/o port 8p82 9p81 10 p80 11 p71/ti0 h general-purpose i/o port. the pin is shared with 16 - bit reload timer ch0 output. 12 p70/to0 general-purpose i/o port. the pin is shared with 16 - bit reload timer ch0 input. 13 mod b an operating mode designation pin 14 x0 a crystal oscillation pin 15 x1 16 vss ? power supply pin (gnd) 17 vcc ? power supply pin 18 pg0 h general-purpose i/o port. 19 pg2/x1a h/a single-system product is general-purpose port. dual-system product is crystal oscillation pin (32 khz). 20 pg1/x0a 21 rst b? reset pin 22 p00/int00 c general-purpose i/o port. the pins are shared with external interrupt input. large current port. 23 p01/int01 24 p02/int02 25 p03/int03 26 p04/int04 27 p05/int05 28 p06/int06 29 p07/int07 30 p10/ui0 g general-purpose i/o port. the pin is shared with uart/sio ch0 data input.
mb95100a series 9 (continued) pin no. pin name circuit type description 31 p11/uo0 h general-purpose i/o port. the pin is shared with uart/sio ch0 data output. 32 p12/uck0 general-purpose i/o port. the pin is shared with uart/sio ch0 clock i/o. 33 p13/trg0/ adtg general-purpose i/o port. the pin is shared with 16-bit ppg ch0 trigger input (trg0) and a/d trigger input (adtg). 34 p14/ppg0 general-purpose i/o port. the pin is shared with 16-bit ppg ch0 output. 35 p20/ppg00 h general-purpose i/o port. the pins are shared with 8/16-bit ppg ch0 output. 36 p21/ppg01 37 p22/to00 general-purpose i/o port. the pins are shared with 8/16 -bit compound timer ch0 output. 38 p23/to01 39 p24/ec0 general-purpose i/o port. the pin is shared with 8/16-bit compound timer ch0 clock input. 40 p50/scl0 i general-purpose i/o port. the pin is shared with i 2 c ch0 clock i/o. 41 p51/sda0 general-purpose i/o port. the pin is shared with i 2 c ch0 data i/o. 42 p52/ppg1 h general-purpose i/o port. the pin is shared with 16-bit ppg ch1 output. 43 p53/trg1 general-purpose i/o port. the pin is shared with 16-bit ppg ch1 trigger input. 44 p60/ppg10 k general-purpose i/o port. the pins are shared with 8/16-bit ppg ch1 output. 45 p61/ppg11 46 p62/to10 general-purpose i/o port. the pins are shared with 8/16 -bit compound timer ch1 output. 47 p63/to11 48 p64/ec1 general-purpose i/o port. the pin is shared with 8/16-bit compound timer ch1 clock input. 49 p65/sck general-purpose i/o port. the pin is shared with lin-uart clock i/o. 50 p66/sot general-purpose i/o port. the pin is shared with lin-uart data output. 51 p67/sin l general-purpose i/o port. the pin is shared with lin-uart data input. 52 p43/an11 j general-purpose i/o port. the pins are shared with a/d analog input. 53 p42/an10 54 p41/an09 55 p40/an08
mb95100a series 10 (continued) pin no. pin name circuit type description 56 p37/an07 j general-purpose i/o port. the pins are shared with a/d analog input. 57 p36/an06 58 p35/an05 59 p34/an04 60 p33/an03 61 p32/an02 62 p31/an01 63 p30/an00 64 avss ? a/d power supply pin (gnd)
mb95100a series 11 i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed side feedback resistance value : approx. 1 m ? low-speed side feedback resistance : approx. 24 m ? (eva product : approx. 10 m ? ) dumping resistance : approx. 144 k ? (eva product : without dumping resistance) b only for input hysteresis input only for mask product with pull-down resistor only for mask product b? hysteresis input only for mask product c cmos output hysteresis input g cmos output cmos input hysteresis input with pull - up control h cmos output hysteresis input with pull - up control x 0 (x0a) x1 (x1a) standby control r pch nch standby control external interrupt enable r pch nch pull-up control standby control pch nch r pull-up control standby control
mb95100a series 12 (continued) type circuit remarks i nch open drain output cmos input hysteresis input j cmos output hysteresis input analog input with pull - up control k cmos output hysteresis input l cmos output cmos input hysteresis input o nch open drain output hysteresis input p cmos output hysteresis input with pull - up control nch standby control r pch nch pull-up control a/d control standby control analog input pch nch standby control pch nch standby control nch standby control r pch nch standby control external interrupt control pull-up control
mb95100a series 13 handling devices ? preventing latchup care must be taken to ensure that maximum vo ltage ratings are not ex ceeded when they are used. latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between v cc and v ss . when latchup occurs, power supply current increa ses rapidly and might thermally damage elements. also, take care to prevent the analog power supply voltage (av cc , avr) and analog input voltage from exceeding the digital power supply voltage (v cc ) when the analog system power supply is turned on or off. ? stable supply voltage supply voltage should be stabilized. a sudden change in power-supply voltage may cause a ma lfunction even within the guaranteed operating range of the vcc power-supply voltage. for stabilization, in principle, keep the variation in vcc ripple (p-p value) in a commercial frequency range (50 hz to 60 hz) not to exceed 10% of the vcc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 v/ms during a mom entary change such as when the power supply is switched. ? treatment of unused input pin an unused input pin may cause a malfunction if it is le ft open. it should be connected to a pull-up or pull-down resistor. ? treatment of power supply pins on a/d converter connect to be av cc = v cc and av ss = avr = v ss even if the a/d converter is not in use. ? precautions for use of external clock even when an external clock is used, oscillation stabilizat ion wait time is required for power-on reset, wake-up from subclock mode or stop mode. ? precaution against noise to the external reset pin (rst ) an input of a reset pulse below the specified level to the external reset pin (rst ) may cause malfunctions. be sure not to allow an input of a reset pulse below the specified level to the external reset pin (rst ).
mb95100a series 14 programming flash microcontrollers using parallel programmer ? supported parallel programmers and adapters the following table lists supported parallel programmers and adapters. notes: ? set all of the j1 to j3 switc hes on the adapter to "95f108". ? for information on applicable adapter models and parallel programmers, contact the following: flash support group, inc. tel: 053-428-8380 ? sector configuration the individual sectors of flash memory correspond to add resses used for cpu access and programming by the parallel programmer as follows: ? programming method 1) set the type code of the parallel programmer to 17226. 2) load program data to programmer addresses 71000 h to 7ffff h . 3) programmed by parallel programmer package applicable adapter model parallel programmers fpt-64p-m03 tef110-108f35ap af9708 (ver 02.35g or more) af9709/b (ver 02.35g or more) af9723+af9834 (ver 02.08e or more) fpt-64p-m09 tef110-108f36ap *: programmer addresses are equivalent to cpu addre sses, used when the parallel programmer programs data into flash memory. these programmer addresses are used for the parallel programmer to program or erase data in flash memor y. flash memory cpu address writer address* sa1 (4 kbytes) 1000 h 71000 h 1fff h 71fff h sa2 (4kbytes) 2000 h 72000 h 2fff h 72fff h sa3 (4 kbytes) 3000 h 73000 h 3fff h 73fff h sa4 (16 kbytes) 4000 h 74000 h 7fff h 77fff h sa5 (16 kbytes) 8000 h 78000 h bfff h 7bfff h sa6 (4 kbytes) c000 h 7c000 h cfff h 7cfff h sa7 (4 kbytes) d000 h 7d000 h dfff h 7dfff h sa8 (4 kbytes) e000 h 7e000 h efff h 7efff h sa9 (4 kbytes) f000 h 7f000 h ffff h 7ffff h lower bank upper bank
mb95100a series 15 block diagram p80 ~ p83 p14/ppg0 p53/trg1 p65/sck p67/sin pe0/int10 ~ pe3/int1 3 av cc av ss avr p52/ppg1 p50/scl0 p51/sda0 p40/an08 ~ p43/an11 p30/an00 ~ p37/an07 p21/ppg01 p22/to00 p23/to01 p24/ec0 p12/uck0 p62/to10 p61/ppg11 p60/ppg10 p63/to11 p 00/int00 ~ p07/int07 p10/ui0 p64/ec1 p71/ti0 p66/sot p70/to0 rst x0,x1 pg2/x1a* pg1/x0a* pg0 mod, v cc , v ss p13/trg0/adtg p20/ppg00 p11/uo0 i 2 c f 2 mc-8fx cpu uart/sio 16 bit-ppg ch0 8/16-bit ppg ch0 10-bit a/d converter c 16-bit ppg ch1 lin-uart 8/16-bit ppg ch1 rom ram port port external interrupt ch8 to ch11 8/16-bit compound timer ch0 16-bit reload timer 8/16-bit compound timer ch1 interrupt control wild register reset control clock control watch prescaler watch counter external interrupt ch0 to ch7 internal bus * : single-system product is general-purpose port, and dual-system product is subclock oscillation. other pins
mb95100a series 16 cpu core 1. memory space memory space of the mb95100a series is 64 kbytes and consists of i/o area, data area, and program area. the memory space includes special - purpose areas such as the general - purpose registers and vector table. memory map of the mb95100a series is shown in below. memory map 0000 h 0080 h 0100 h 0200 h 0f80 h 1000 h ffff h i/o flash 60 kb ram 3.75 kb mb95fv100a-10 1 i/o 0000 h 0080 h 0100 h 0200 h 0880 h 0f80 h 1000 h ffff h flash 60 kb mb95f108a i/o ram 2 kb i/o 0 000 h 0 080 h 0 100 h 0 200 h 0 880 h 0 f80 h 1 000 h 4 000 h f fff h rom 48 kb MB95107A i/o ram 2 kb i/o register register access prohibited access prohibited access prohibited register
mb95100a series 17 2. register the mb95100a series has two types of registers; dedica ted registers in the cpu and general-purpose registers in the memory. the dedicated registers are as follows: the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and a direct bank pointer (dp) and the lower 8 bits for use as a conditi on code register (ccr) . (see the diagram below.) program counter (pc) : a 16-bit register to indi cate locations where instructions are stored. accumulator (a) : a 16-bit register for temporary st orage of arithmetic oper ations. in the case of an 8-bit data processing instruction, the lower one byte is used. temporary accumulator (t) : a 16-bit register which pe rforms arithmetic operations with the accumulator. in the case of an 8-bit data processing instruction, the lower one byte is used. index register (ix) : a 16-bit register for index modification extra pointer (ep) : a 16-bit pointer to point to a memory address. stack pointer (sp) : a 16-bit register to indicate a stack area. program status (ps) : a 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register pc a t ix ep sp ps : program counter 16-bit : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status initial value fffd h 0000 h 0000 h 0000 h 0000 h 0000 h 0030 h p s rp ccr 15 14 13 12 11 10 9 8 dp2 dp1 dp0 7654321 0 r4 r3 r2 r1 r0 h i il1 il0 n z v c dp ? structure of the program status
mb95100a series 18 the rp indicates the address of th e register bank currently being used . the relationship between the content of rp and the real address conforms to the conversion rule illustrated below: the dp specifies the area for mapping instructions (16 di fferent instructions such as mov a, dir) using direct addresses to 0080 h to 00ff h . the ccr consists of the bits indicating arithmetic opera tion results or transfer data contents and the bits that control cpu operations at interrupt. direct bank pointer (dp2 to dp0) specified address area mapping area don?t care 0000 h to 007f h 0000 h to 007f h (without mapping) 000 b (initial value) 0080 h to 00ff h 0080 h to 00ff h (without mapping) 001 b 0100 h to 017f h 010 b 0180 h to 01ff h 011 b 0200 h to 027f h 100 b 0280 h to 02ff h 101 b 0300 h to 037f h 110 b 0380 h to 03ff h 111 b 0400 h to 047f h h flag : set to ?1? when a carry or a borrow from bit 3 to bi t 4 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. this flag is for decimal adjustment instructions. i flag : interrupt is enabled when this flag is set to ?1?. in terrupt is disabled when this flag is set to ?0?. the flag is set to ?0? when reset. il1, il0 : indicates the level of the interrupt currently enabled. processes an inte rrupt only if its request level is higher than the value indicated by this bit. il1 il0 interrupt level priority 00 0 high low = no interruption 01 1 10 2 11 3 n flag : set to ?1? if the msb is set to ?1? as the result of an arithmetic operation. cleared to ?0? when the bit is set to ?0?. z flag : set to ?1? when an arithmetic operation results in 0. cleared to ?0? otherwise. v flag : set to ?1? if the complement on 2 overflows as a re sult of an arithmetic operation. cleared to ?0? otherwise. c flag : set to ?1? when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. set to the shift-out va llue in the case of a shift instruction. "0" "0" "0" "0" "0" "0" "0" "1" r4 r3 r2 r1 r0 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 a15 a14 a13 a12 a11 a10 a9 a8 ? rule for conversion of actual addresse s in the general-purpose register area generated address rp upper op code lower
mb95100a series 19 the following general-purpose registers are provided: general-purpose registers: 8-bit data storage registers the general-purpose registers are 8 bits and located in the register banks on the memory. one bank contains eight registers. up to a total of 32 banks can be used on the mb95100a series. the bank currently in use is indicated by the register bank pointer (rp). r0 r1 r2 r3 r4 r5 r6 r7 register bank configuration this address = 0100 h + 8 x (rp) 32 banks memory area
mb95100a series 20 i/o map (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (vacancy) ?? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w 1010x011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r xxxxxxxx b 000a h tbtc timebase timer control register r/w 0000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h ? (vacancy) ?? 000e h pdr2 port 2 data register r/w 00000000 b 000f h ddr2 port 2 direction register r/w 00000000 b 0010 h pdr3 port 3 data register r/w 00000000 b 0011 h ddr3 port 3 direction register r/w 00000000 b 0012 h pdr4 port 4 data register r/w 00000000 b 0013 h ddr4 port 4 direction register r/w 00000000 b 0014 h pdr5 port 5 data register r/w 00000000 b 0015 h ddr5 port 5 direction register r/w 00000000 b 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h pdr7 port 7 data register r/w 00000000 b 0019 h ddr7 port 7 direction register r/w 00000000 b 001a h pdr8 port 8 data register r/w 00000000 b 001b h ddr8 port 8 direction register r/w 00000000 b 001c h to 0025 h ? (vacancy) ?? 0026 h pdre port e data register r/w 00000000 b 0027 h ddre port e direction register r/w 00000000 b 0028 h ? (vacancy) ?? 0029 h 002a h pdrg port g data register r/w 00000000 b
mb95100a series 21 (continued) address register abbreviation register name r/w initial value 002b h ddrg port g direction register r/w 00000000 b 002c h ? (vacancy) ?? 002d h pul1 port 1 pull - up register r/w 00000000 b 002e h pul2 port 2 pull - up register r/w 00000000 b 002f h pul3 port 3 pull - up register r/w 00000000 b 0030 h pul4 port 4 pull - up register r/w 00000000 b 0031 h pul5 port 5 pull - up register r/w 00000000 b 0032 h pul7 port 7 pull - up register r/w 00000000 b 0033 h ? (vacancy) ?? 0034 h pule port e pull - up register r/w 00000000 b 0035 h pulg port g pull - up register r/w 00000000 b 0036 h t01cr1 8/16-bit compound timer 01 contro l status register 1 ch0 r/w 00000000 b 0037 h t00cr1 8/16-bit compound timer 00 contro l status register 1 ch0 r/w 00000000 b 0038 h t11cr1 8/16-bit compound timer 11 contro l status register 1 ch1 r/w 00000000 b 0039 h t10cr1 8/16-bit compound timer 10 contro l status register 1 ch1 r/w 00000000 b 003a h pc01 8/16-bit ppg1 control register ch0 r/w 00000000 b 003b h pc00 8/16-bit ppg0 control register ch0 r/w 00000000 b 003c h pc11 8/16-bit ppg1 control register ch1 r/w 00000000 b 003d h pc10 8/16-bit ppg0 control register ch1 r/w 00000000 b 003e h tmcsrh0 16-bit reload timer control stat us register (upper byte) ch0 r/w 00000000 b 003f h tmcsrl0 16-bit reload timer control status register (lower byte) ch0 r/w 00000000 b 0040 h ? (vacancy) ?? 0041 h 0042 h pcnth0 16-bit ppg control status r egister (upper byte) ch0 r/w 00000000 b 0043 h pcntl0 16-bit ppg control status r egister (lower byte) ch0 r/w 00000000 b 0044 h pcnth1 16-bit ppg control status r egister (upper byte) ch1 r/w 00000000 b 0045 h pcntl1 16-bit ppg control status r egister (lower byte) ch1 r/w 00000000 b 0046 h ? (vacancy) ?? 0047 h 0048 h eic00 external interrupt circuit control register ch0/1 r/w 00000000 b 0049 h eic10 external interrupt circuit control register ch2/3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch4/5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch6/7 r/w 00000000 b 004c h eic01 external interrupt circuit control register ch8/9 r/w 00000000 b 004d h eic11 external interrupt circuit co ntrol register ch10/11 r/w 00000000 b
mb95100a series 22 (continued) address register abbreviation register name r/w initial value 004e h ? (vacancy) ?? 004f h 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uartserial status register r/w 00001000 b 0053 h rdr/tdr lin-uart reception/transmission data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communicat ion control register r/w 000000xx b 0056 h smc10 uart/sio serial mode c ontrol register 1 ch0 r/w 00000000 b 0057 h smc20 uart/sio serial mode control register 2 ch0 r/w 00100000 b 0058 h ssr0 uart/sio serial status register ch0 r/w 00000001 b 0059 h tdr0 uart/sio serial output data register ch0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch0 r 00000000 b 005b h to 005f h ? (vacancy) ?? 0060 h ibcr00 i 2 c bus control register 0 ch0 r/w 00000000 b 0061 h ibcr10 i 2 c bus control register 1 ch0 r/w 00000000 b 0062 h ibsr0 i 2 c bus status register ch0 r 00000000 b 0063 h iddr0 i 2 c data register ch0 r/w 00000000 b 0064 h iaar0 i 2 c address register ch0 r/w 00000000 b 0065 h iccr0 i 2 c clock control register ch0 r/w 00000000 b 0066 h to 006b h ? (vacancy) ?? 006c h adc1 a/d control register 1 r/w 00000000 b 006d h adc2 a/d control register 2 r/w 00000000 b 006e h addh a/d data register (upper byte) r/w 00000000 b 006f h addl a/d data register (lower byte) r/w 00000000 b 0070 h wcsr watch counter status register r/w 00000000 b 0071 h ? (vacancy) ?? 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector writ ing control register 0 r/w 00000000 b 0074 h swre1 flash memory sector writ ing control register 1 r/w 00000000 b 0075 h ? (vacancy) ?? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b
mb95100a series 23 (continued) address register abbreviation register name r/w initial value 0078 h ? (mirror of register bank pointer (rp) and direct bank pointer (dp) ) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (vacancy) ?? 0f80 h wrarh0 wild register address setting register (upper byte) ch0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower byte) ch0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper byte) ch1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower byte) ch1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper byte) ch2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower byte) ch2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch2 r/w 00000000 b 0f89 h to 0f91 h ? (vacancy) ?? 0f92 h t01cr0 8/16-bit compound timer 01 contro l status register 0 ch0 r/w 00000000 b 0f93 h t00cr0 8/16-bit compound timer 00 contro l status register 0 ch0 r/w 00000000 b 0f94 h t01dr 8/16-bit compound timer 01 data register ch0 r/w 00000000 b 0f95 h t00dr 8/16-bit compound timer 00 data register ch0 r/w 00000000 b 0f96 h tmcr0 8/16-bit compound timer 00/01 timer mode control register ch0 r/w 00000000 b 0f97 h t11cr0 8/16-bit compound timer 11 contro l status register 0 ch1 r/w 00000000 b 0f98 h t10cr0 8/16-bit compound timer 10 contro l status register 0 ch1 r/w 00000000 b 0f99 h t11dr 8/16-bit compound timer 11 data register ch1 r/w 00000000 b 0f9a h t10dr 8/16-bit compound timer 10 data register ch1 r/w 00000000 b 0f9b h tmcr1 8/16-bit compound timer 10/11 timer mode control register ch1 r/w 00000000 b 0f9c h pps01 8/16-bit ppg1 cycle setti ng buffer register ch0 r/w 11111111 b 0f9d h pps00 8/16-bit ppg0 cycle setti ng buffer register ch0 r/w 11111111 b 0f9e h pds01 8/16-bit ppg1 duty setting buffer register ch0 r/w 11111111 b 0f9f h pds00 8/16-bit ppg0 duty setting buffer register ch0 r/w 11111111 b
mb95100a series 24 (continued) address register abbreviation register name r/w initial value 0fa0 h pps11 8/16-bit ppg1 cycle setting buffer register ch1 r/w 11111111 b 0fa1 h pps10 8/16-bit ppg0 cycle setting buffer register ch1 r/w 11111111 b 0fa2 h pds11 8/16-bit ppg1 duty setting buffer register ch1 r/w 11111111 b 0fa3 h pds10 8/16-bit ppg0 duty setting buffer register ch1 r/w 11111111 b 0fa4 h ppgs 8/16-bit ppg start register r/w 00000000 b 0fa5 h revc 8/16-bit ppg output inversion register r/w 00000000 b 0fa6 h tmrh0/ tmrlrh0 16-bit timer register (upper byte) ch0/ 16-bit reload register (upper byte) ch0 r/w 00000000 b 0fa7 h tmrl0/ tmrlrl0 16-bit timer register (lower byte) ch0/ 16-bit reload register (lower byte) ch0 r/w 00000000 b 0fa8 h ? (vacancy) ?? 0fa9 h 0faa h pdcrh0 16-bit ppg down counter regi ster (upper byte) ch0 r 00000000 b 0fab h pdcrl0 16-bit ppg down counter regi ster (lower byte) ch0 r 00000000 b 0fac h pcsrh0 16-bit ppg cycle setting buffer register (upper byte) ch0 r/w 11111111 b 0fad h pcsrl0 16-bit ppg cycle setting buffer register (lower byte) ch0 r/w 11111111 b 0fae h pduth0 16-bit ppg duty setting buffer register (upper byte) ch0 r/w 11111111 b 0faf h pdutl0 16-bit ppg duty setting buffer register (lower byte) ch0 r/w 11111111 b 0fb0 h pdcrh1 16-bit ppg down counter regi ster (upper byte) ch1 r 00000000 b 0fb1 h pdcrl1 16-bit ppg down counter regi ster (lower byte) ch1 r 00000000 b 0fb2 h pcsrh1 16-bit ppg cycle setting buffer register (upper byte) ch1 r/w 11111111 b 0fb3 h pcsrl1 16-bit ppg cycle setting buffer register (lower byte) ch1 r/w 11111111 b 0fb4 h pduth1 16-bit ppg duty setting buffer registe ( upper byte ) ch1 r/w 11111111 b 0fb5 h pdutl1 16-bit ppg duty setting buffer register ( lower byte ) ch1 r/w 11111111 b 0fb6 h to 0fbb h ? (vacancy) ?? 0fbc h bgr1 lin-uart baud rate gener ator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h pssr0 uart/sio prescaler selection register ch0 r/w 00000000 b 0fbf h brsr0 uart/sio baud rate setting register ch0 r/w 00000000 b 0fc0 h ? (vacancy) ?? 0fc1 h 0fc2 h aidrh a/d input disable register (upper byte) r/w 00000000 b 0fc3 h aidrl a/d input disable regist er (lower byte) r/w 00000000 b 0fc4 h to 0fe2 h ? (vacancy) ??
mb95100a series 25 (continued) ? read/write access symbols ? initial value symbols address register abbreviation register name r/w initial value 0fe3 h wcdr watch counter data register r/w 00111111 b 0fe4 h to 0fed h ? (vacancy) ?? 0fee h ilsr input level select register r/w 00000000 b 0fef h wicr interrupt pin control register r/w 01000000 b 0ff0 h to 0fff h ? (vacancy) ?? r/w : readable and writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95100a series 26 interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register same level priority order (at simultaneous occurrence) upper lower external interrupt ch0 irq0 fffa h fffb h l00 [1 : 0] high external interrupt ch4 external interrupt ch1 irq1 fff8 h fff9 h l01 [1 : 0] external interrupt ch5 external interrupt ch2 irq2 fff6 h fff7 h l02 [1 : 0] external interrupt ch6 external interrupt ch3 irq3 fff4 h fff5 h l03 [1 : 0] external interrupt ch7 uart/sio ch0 irq4 fff2 h fff3 h l04 [1 : 0] 8/16-bit compound timer ch0 (lower) irq5 fff0 h fff1 h l05 [1 : 0] 8/16-bit compound timer ch0 (upper) irq6 ffee h ffef h l06 [1 : 0] lin-uart (reception) irq7 ffec h ffed h l07 [1 : 0] lin-uart (transmission) irq8 ffea h ffeb h l08 [1 : 0] 8/16-bit ppg ch1 (lower) irq9 ffe8 h ffe9 h l09 [1 : 0] 8/16-bit ppg ch1 (upper) irq10 ffe6 h ffe7 h l10 [1 : 0] 16-bit reload timer ch0 irq11 ffe4 h ffe5 h l11 [1 : 0] 8/16-bit ppg ch0 (upper) irq12 ffe2 h ffe3 h l12 [1 : 0] 8/16-bit ppg ch0 (lower) irq13 ffe0 h ffe1 h l13 [1 : 0] 8/16-bit compound timer ch1 (upper) irq14 ffde h ffdf h l14 [1 : 0] 16-bit ppg ch0 irq15 ffdc h ffdd h l15 [1 : 0] i 2 c ch0 irq16 ffda h ffdb h l16 [1 : 0] 16-bit ppg ch1 irq17 ffd8 h ffd9 h l17 [1 : 0] 10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1 : 0] timebase timer irq19 ffd4 h ffd5 h l19 [1 : 0] watch timer/counter irq20 ffd2 h ffd3 h l20 [1 : 0] external interrupt ch8 irq21 ffd0 h ffd1 h l21 [1 : 0] external interrupt ch9 external interrupt ch10 external interrupt ch11 8/16-bit compound timer ch1 (lower) irq22 ffce h ffcf h l22 [1 : 0] flash irq23 ffcc h ffcd h l23 [1 : 0] low
mb95100a series 27 electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 vcc avcc vss ? 0.3 vss + 4.0 v *2 avr vss ? 0.3 vss + 4.0 *2 input voltage* 1 v i1 vss ? 0.3 vss + 4.0 v other than p50, p51, p80 to p83* 3 v i2 vss ? 0.3 vss + 6.0 p50, p51, p80 to p83 output voltage* 1 v o vss ? 0.3 vss + 4.0 v *3 maximum clamp current i clamp ? 2.0 + 2.0 ma applicable to pins* 4 total maximum clamp current |i clamp | ? 20 ma applicable to pins* 4 ?l? level maximum output current i ol1 ? 15 ma other than p00 to p07 i ol2 15 p00 to p07 ?l? level average current i olav1 ? 4 ma other than p00 to p07 average output current = operating current operating ratio (1 pin) i olav2 12 p00 to p07 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma total average output current = operating current operating ratio (total of pins) ?h? level maximum output current i oh1 ? ? 15 ma other than p00 to p07 i oh2 ? 15 p00 to p07 ?h? level average current i ohav1 ? ? 4 ma other than p00 to p07 average output current = operating current operating ratio (1 pin) i ohav2 ? 8 p00 to p07 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? ? 100 ma ?h? level total average output current i ohav ? ? 50 ma total average output current = operating current operating ratio (total of pins)
mb95100a series 28 (continued) *1 : the parameter is based on av ss = v ss = 0.0 v. *2 : apply equal potential to avcc and vcc. avr should not exceed avcc + 0.3 v. *3 : v i1 and vo should not exceed v cc + 0.3 v. v i1 must not exceed the rating voltage. however, if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i1 rating. *4 : applicable to pins : p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p52, p53, p70, p71, pe0 to pe3, pg0 ? use within recommended operating conditions. ? use at dc voltage (current). ? the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does no t exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the powe r saving modes, the +b input potential may pass through the protec tive diode and increase the potentia l at the vcc pin, and this may affect other devices. ? note that if the + b signal is inputted when the mi crocontroller power supply is of f (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting power supply voltage may not be su fficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? sample recommended circuits : warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power consumption pd ? 320 mw operating temperature t a ? 40 + 85 c other than mb95fv100a-101 storage temperature tstg ? 55 + 150 c pch nch vcc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb95100a series 29 2. recommended operating conditions (avss = vss = 0.0 v) *1 : the values vary with the operating frequency. *2 : consult fujitsu separately for a guarantee of a maximum value of 3.6 v. warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc , av cc 1.8* 1 3.3* 2 v at normal operating, flash product, t a = ? 10 c to + 85 c 1.8* 1 3.6 at normal operating, mask product, t a = ? 10 c to + 85 c 2.0* 1 3.3* 2 at normal operating, flash product, t a = ? 40 c to + 85 c 2.0* 1 3.6 at normal operating, mask product, t a = ? 40 c to + 85 c 2.6 3.6 mb95fv100a-101 1.5 3.3* 2 retain status of stop operation, flash product 1.5 3.6 retain status of stop operation, mask product a/d converter reference input voltage avr 1.8 av cc operating temperature t a ? 40 + 85 c other than mb95fv100a-101
mb95100a series 30 3. dc characteristics (vcc = avcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c [mb95fv100a-101 is t a = + 25 c]) (continued) parameter sym- bol pin name condi- tions value unit remarks min typ max ?h? level input voltage v ih1 p10, p67 *1 0.7 vcc ? vcc + 0.3 v at selecting of cmos input level (hysteresis input) v ih2 p50, p51 *1 0.7 vcc ? vss + 5.5 v at selecting of cmos input level (hysteresis input) v ihs1 p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p52, p53, p60 to p67, p70, p71, pe0 to pe3, pg0, pg1* 2 , pg2* 2 *1 0.8 vcc ? vcc + 0.3 v hysteresis input v ihs2 p50, p51, p80 to p83 *1 0.8 vcc ? vss + 5.5 v hysteresis input v ihm rst , mod ? 0.7 vcc ? vcc + 0.3 v cmos input (flash product) ? 0.8 vcc ? vcc + 0.3 v hysteresis input (mask product) ?l? level input voltage v il p10, p50, p51, p67 *1 vss ? 0.3 ? 0.3 vcc v at selecting of cmos input level (hysteresis input) v ils p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p50 to p53, p60 to p67, p70, p71, p80 to p83, pe0 to pe3, pg0, pg1* 2 , pg2* 2 *1 vss ? 0.3 ? 0.2 vcc v hysteresis input v ilm rst , mod ? vss ? 0.3 ? 0.3 vcc v cmos input (flash product) ? vss ? 0.3 ? 0.2 vcc v hysteresis input (mask product) open-drain output application voltage v d p50, p51, p80 to p83 ? vss ? 0.3 ? vss + 5.5 v ?h? level output voltage v oh1 output pin other than p00 to p07 i oh = ? 4.0 ma 2.4 ?? v mb95fv100a-101 a conditional : i oh = ? 2.0 ma v oh2 p00 to p07 i oh = ? 8.0 ma 2.4 ?? v mb95fv100a-101 a conditional : i oh = ? 5.0 ma
mb95100a series 31 (vcc = avcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c [mb95fv100a-101 is t a = + 25 c]) (continued) parameter sym bol pin name conditions value unit remarks min typ max ?l? level output voltage v ol1 output pin other than p00 to p07 i ol = 4.0 ma ?? 0.4 v mb95fv100a-101 a conditional : i ol = 3.0 ma v ol2 p00 to p07 i ol = 12 ma ?? 0.4 v mb95fv100a-101 a conditional : i ol = 8.0 ma input leakage current (high-z output leakage current) i li port other than p50, p51, p80 to p83 0.0 v < v i < vcc ? 5 ? + 5 a when no pull-up resistor is specified open-drain output leakage current i liod p50, p51, p80 to p83 0.0 v < v i < vss + 5.5 v ?? + 5 a pull-up resistor r pull p10 to p14, p20 to p24, p30 to p37, p40 to p43, p52, p53, p70, p71, pe0 to pe3, pg0, pg1* 2 , pg2* 2 v i = 0.0 v 25 50 100 k ? when specifying pull-up resistor pull-down resistor r mod mod v i = vcc 50 100 200 k ? mask product only power supply current* 3 i cc vcc (external clock operation) f ch = 20 mhz fmp = 10 mhz main clock mode (divided by 2) ? 11 14 ma flash product ? 7.3 10 ma mask product ? 30 35 ma flash product (at flash writing and erasing) i ccs f ch = 20 mhz fmp = 10 mhz main sleep mode (divided by 2) ? 4.5 6 ma i ccl f cl = 32 khz fmpl = 16 khz subclock mode (divided by 2) , t a = + 25 c ? 25 35 a i ccls f cl = 32 khz fmpl = 16 khz sub sleep mode (divided by 2) , t a = + 25 c ? 715 a
mb95100a series 32 (continued) (vcc = avcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c [mb95fv100a-101 is t a = + 25 c]) *1 : p10, p50, p51, and p67 can switch the input level to either the cmos input level or hysteresis input level. the switching of the input level can be set by the input level selection register (ilsr). *2 : single-clock product only *3 : the power-supply current is determined by the external clock. ? refer to ?4. ac characteristics (1) clock timing? for f ch and f cl . ? refer to ?4. ac characteristics (2) source clock/machine clock? for fmp and fmpl. parameter sym- bol pin name conditions value unit remarks min typ max power supply current* 3 i cct v cc (external clock operation) f cl = 32 khz watch mode main stop mode t a = + 25 c ? 210 a flash product ? 15 a mask product i ccmpll f ch = 4 mhz fmp = 10 mhz main pll mode (multiplied by 2.5) ? 10 14 ma flash product ? 6.7 10 ma mask product i ccspll f cl = 32 khz fmpl = 128 khz sub pll mode ( multiplied by 4 ) , t a = + 25 c ? 190 250 a i cts f ch = 10 mhz timebase timer mode t a = + 25 c ? 0.4 0.5 ma i cch sub stop mode t a = + 25 c ? 15 a i a avcc f ch = 10 mhz at operating of a/d conversion ? 1.3 2.2 ma i ah f ch = 10 mhz at stopping a/d conversion t a = + 25 c ? 15 a input capacitance c in other than avcc, avss, avr, vcc, vss ?? 515pf
mb95100a series 33 4. ac characteristics (1) clock timing (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin condi- tions value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 10 mhz when using main oscilla- tion circuit 1 ? 20 mhz when using external clock 3 ? 10 mhz main pll multiplied by 1 3 ? 5 mhz main pll multiplied by 2 3 ? 4 mhz main pll multiplied by 2.5 f cl x0a, x1a ? 32.768 ? khz when using sub oscilla- tion circuit ? 32.768 ? khz when using sub pll flash product : vcc = 2.3 v to 3.3 v mask product : vcc = 2.3 v to 3.6 v clock cycle time t hcyl x0, x1 100 ? 1000 ns when using main oscilla- tion circuit 50 ? 1000 ns when using external clock t lcyl x0a, x1a ? 30.5 ? s when using sub oscilla- tion circuit input clock pulse width t wh1 t wl1 x0 10 ?? ns when using external clock duty ratio is about 30 % to 70 % . t wh2 t wl2 x0a ? 15.2 ? s input clock rise time and fall time t cr t cf x0, x0a ?? 5 ns when using external clock
mb95100a series 34 t hcyl t wh1 t cr 0.2 v cc x 0 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl1 x0 x1 f ch x0 f ch x1 ? x0 and x1 timing and applying conditions ? main clock applying conditions when using a crystal or ceramic oscillator when using external clock open t lcyl t wh2 t cr 0.1 v cc x 0a 0.8 v cc 0.8 v cc 0.1 v cc 0.1 v cc t cf t wl2 x0a x1a f cl x0a f cl x1a ? x0a and x1a timing and applying conditions ? subclock applying conditions when using a crystal or ceramic oscillator when using external clock open
mb95100a series 35 (2) source clock/machine clock (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : clock before setting division due to machine clock divi sion ratio selection bit (sycc : div1 and div0) . this source clock is divided by the machin e clock division ratio selection bit (sycc : div1 and div0) , and it becomes the machine clock. further, the source clock can be selected as follow. ? main clock divided by 2 ? pll multiplication of main clock (sel ect from 1, 2, 2.5 multiplication) ? subclock divided by 2 ? pll multiplication of subclock (sel ect from 2, 3, 4 multiplication) * 2 : operation clock of the microcontroller. machine clock can be selected as follow. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter sym- bol pin name value unit remarks min typ max source clock* 1 (clock before setting division) sclk ? 100 ? 2000 ns when using main clock min : f ch = 10 mhz, pll multiplied by 1 max : f ch = 1 mhz, divided by 2 7.6 ? 61.0 s when using subclock min : f cl = 32 khz, pll multiplied by 4 max : f cl = 32 khz, divided by 2 source clock frequency fsp ? 0.5 ? 10.0 mhz when using main clock fspl ? 16.384 ? 131.072 khz when using subclock machine clock* 2 (minimum instruction execution time) mclk ? 100 ? 32000 ns when using main clock min : slck = 10 mhz, no division max : slck = 0.5 mhz, divided by 16 7.6 ? 976.5 s when using subclock min : slck = 131 khz, no division max : slck = 16 khz, divided by 16 machine clock frequency fmp ? 0.031 ? 10.000 mhz when using main clock fmpl 1.024 ? 131.072 khz when using subclock
mb95100a series 36 (continued) ? mask product ? flash product note: in operating by 2.0 v or less, only ?t a = -10 c to +85 c? is guaranteed. 10 mhz 0.5 mhz 1.0 3.6 2.2 1.8 5 mhz 3 mhz 2.0 sub pll operation guarantee range (2.3 v to 3.6 v) a/d converter accuracy guarantee range operating voltage (v) source clock frequency (fsp) main pll operation guarantee range 10 mhz 0.5 mhz 1.0 3.3 2.2 1.8 5 mhz 3 mhz 2.0 sub pll operation guarantee range (2.3 v to 3.3 v) a/d converter accuracy guarantee range operating voltage (v) source clock frequency (fsp) main pll operation guarantee range ? operating voltage - operating frequency
mb95100a series 37 (continued) 10 mh z 4 mhz 3 mhz 5 mhz 6 mhz 7 mhz 8 mhz 9 mhz 3 mhz 4 mhz 5 mhz 6 mhz 7 mhz 8 mhz 9 mhz 10 mhz 7 .5 mhz ? main pll operation frequency main clock frequency source clock frequency (fsp) 2.5 2 1
mb95100a series 38 (3) reset timing (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : refer to ? (2) source clock/machine clock? for mclk. *2 : oscillation time of oscillator is the time that the amp litude reaches 90 %. in the crystal oscillator, the oscillation time is between several ms and tens of ms. in far/cera mic oscillators, the oscillation time is between hundreds of s and several ms. in the external clock, the oscillation time is 0 ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 mclk* 1 ? ns at normal operating oscillation time of oscillator* 2 + 2 mclk* 1 ? ns at stop mode, subclock mode, sub sleep mode, and watch mode t rstl 0.2 v cc rst 0.2 v cc t rstl 0.2 v cc 0.2 v cc 2 mclk rst x0 ? at normal operating ? at stop mode, subclock mode , sub sleep mode, and watch mode internal operating clock internal reset 90 % of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction
mb95100a series 39 (4) power-on reset (avss = vss = 0.0 v, t a = ? 40 c to + 85 c) note : the power supply must be turned on within the selected oscillation stabilization time. parameter symbol conditions value unit remarks min max power supply rising time t r ?? 36 ms power supply cutoff time t off ? 1 ? ms due to repeated operations 0.2 v 0.2 v t off t r 1.5 v 0.2 v v cc v cc 1 .5 v v ss sudden change of power supply voltag e may activate the power-on reset function. when changing power supply voltages during operation, set the slope of rising within 20 mv/ms as show n below. in this case, do not use pll clock. however, if voltage drop is 1v/s or less, use of pll clock is allowed during operation. ram data hold period limiting the slope of rising within 20 mv/ms is recommended.
mb95100a series 40 (5) peripheral input timing (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for mclk. parameter symbol pin name value unit remarks min max peripheral input ?h? pulse width t ilih int00 to int07, int10 to int13, ec0, ec1, ti0, trg0/adtg, trg1 2 mclk* ? ns peripheral input ?l? pulse width t ihil 2 mclk* ? ns t ilih i nt00 to int07, i nt10 to int13, ec0, ec1, t i0, trg0/adtg, trg1 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ihil
mb95100a series 41 (6) uart/sio, serial i/o timing (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for mclk. parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc uck0 internal clock operation 4 mclk* ? ns uck uo time t slov uck0, uo0 ? 190 190 ns valid ui uck t ivsh uck0, ui0 2 mclk* ? ns uck valid ui hold time t shix uck0, ui0 2 mclk* ? ns serial clock ?h? pulse width t shsl uck0 external clock operation 4 mclk* ? ns serial clock ?l? pulse width t slsh uck0 4 mclk* ? ns uck uo time t slov uck0, uo0 ? 190 ns valid ui uck t ivsh uck0, ui0 2 mclk* ? ns uck valid ui hold time t shix uck0, ui0 2 mclk* ? ns t scyc t ivsh v ih v il v ih v il t shix t slov 0.8 v 2.4 v 0.8 v 2.4 v u ck0 u o0 u i0 0.8 v t slsh t ivsh v ih v il v ih v il t shix t slov 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t shsl 2.4 v u ck0 u o0 u i0 0.8 v internal shift clock mode external shift clock mode
mb95100a series 42 (7) lin-uart timing escr : sces = 0, eccr : scde = 0 (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for mclk. parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl 5 mclk* ? ns sck sot delay time t slovi sck, sot ? 95 95 ns valid sin sck t ivshi sck, sin mclk* + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin : c l = 80 pf + 1 ttl 3 mclk* ? t r ? ns serial clock ?h? pulse width t shsl sck mclk* + 95 ? ns sck sot delay time t slove sck, sot ? 2 mclk* + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin mclk* + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95100a series 43 0.8 v 2.4 v t slovi t ivshi t shixi v ih v il 2.4 v 0.8 v s ck s ot s in t scyc v il v ih t slove t ivshe t shixe v ih v il 2.4 v 0.8 v t r t f s ck s ot s in t slsh t shsl internal shift clock mode external shift clock mode
mb95100a series 44 escr : sces = 1, eccr : scde = 0 (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for mclk. parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl 5 mclk* ? ns sck sot delay time t shovi sck, sot ? 95 95 ns valid sin sck t ivsli sck, sin mclk* + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin : c l = 80 pf + 1 ttl 3 mclk* ? t r ? ns serial clock ?l? pulse width t slsh sck mclk* + 95 ? ns sck sot delay time t shove sck, sot ? 2 mclk* + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin mclk* + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95100a series 45 0.8 v 2.4 v t shovi t ivsli t slixi v ih v il 2.4 v 0.8 v s ck s ot s in t scyc v il v ih t shove t ivsle t slixe v ih v il 2.4 v 0.8 v t f t r s ck s ot s in t shsl t slsh internal shift clock mode external shift clock mode
mb95100a series 46 escr : sces = 0, eccr : scde = 1 (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for mclk. parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl 5 mclk* ? ns sck sot delay time t shovi sck, sot ? 95 95 ns valid sin sck t ivsli sck, sin mclk* + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 mclk* ns s ck s ot s in 2.4 v 0.8 v 0.8 v t shovi 2.4 v 0.8 v v ih v il v ih v il 2.4 v 0.8 v t scyc t sovli t ivsli t slixi
mb95100a series 47 escr : sces = 1, eccr : scde = 1 (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for mclk. parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operating output pin : c l = 80 pf + 1 ttl 5 mclk* ? ns sck sot hold time t slovi sck, sot ? 95 95 ns valid sin sck t ivshi sck, sin mclk* + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 mclk* ns s ck s ot s in 2.4 v 2.4 v 0.8 v t slovi 2.4 v 0.8 v v ih v il v ih v il 2.4 v 0.8 v t scyc t sovhi t ivshi t shixi
mb95100a series 48 (8) i 2 c timing (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hd;dat have only to be met if the device dose not stretch the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. parameter symbol conditions value unit remarks standard-mode fast-mode min max min max scl clock frequency f scl r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz (repeat) start condition hold time sda scl t hd;sta 4.0 ? 0.6 ? s scl clock ?l? width t low 4.7 ? 1.3 ? s scl clock ?h? width t high 4.0 ? 0.6 ? s (repeat) start condition setup time scl sda t su;sta 4.7 ? 0.6 ? s data hold time scl sda t hd;dat 03.45* 2 00.9* 3 s data setup time sda scl t su;dat 0.25 ? 0.1 ? s stop condition setup time scl sda t su;sto 4 ? 0.6 ? s bus free time between stop condition and start condition t buf 4.7 ? 1.3 ? s sda0 scl0 t wakeup t hd;sta t hd;dat t hd;sta t su;sta t low t su;dat t high t su;sto t buf
mb95100a series 49 (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol i/o timing unit remarks min max scl clock ?l? width t low (2 + nm* 2 / 2) mclk* 1 ? 20 ? ns master mode scl clock ?h? width t high (nm* 2 / 2) mclk* 1 ? 20 (nm* 2 / 2 ) mclk* 1 + 20 ns master mode start condition hold time t hd;sta ( ? 1 + nm* 2 / 2) mclk* ?1 ? 20 ( ? 1 + nm* 2 ) mclk* 1 + 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto (1 + nm* 2 / 2) mclk* ?1 ? 20 (1 + nm* 2 / 2) mclk* 1 + 20 ns master mode start condition setup time t su;sta (1 + nm* 2 / 2) mclk* 1 ? 20 (1 + nm* 2 / 2) mclk* 1 + 20 ns master mode bus free time between stop condition and start condition t buf (2 nm* 2 + 4) mclk* 1 ? 20 ? ns data hold time t hd;dat 3 mclk* 1 ? 20 ? ns master mode data setup time t su;dat ( ? 2 + nm* 2 / 2) mclk* 1 ? 20 ( ? 1 + nm* 2 / 2) mclk* 1 + 20 ns master mode when assuming that ?l? of scl is not extended, the minimum value is applied to first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int (nm* 2 / 2) mclk* 1 ? 20 (1 + nm* 2 / 2) mclk* 1 + 20 ns minimum value is applied to interrupt at 9th scl . maximum value is applied to interrupt at 8th scl . scl clock ?l? width t low 4 mclk* 1 ? 20 ? ns at reception scl clock ?h? width t high 4 mclk* 1 ? 20 ? ns at reception start condition detection t hd;sta 2 mclk* 1 ? 20 ? ns undetected when 1 mclk is used at reception stop condition detection t su;sto 2 mclk* 1 ? 20 ? ns undetected when 1 mclk is used at reception restart condition detection condition t su;sta 2 mclk* 1 ? 20 ? ns undetected when 1 mclk is used at reception bus free time t buf 2 mclk* 1 ? 20 ? ns at reception data hold time t hd;dat 2 mclk* 1 ? 20 ? ns at slave transmission mode data setup time t su;dat t low ? 3 mclk* 1 ? 20 ? ns at slave transmission mode data hold time t hd;dat 0 ? ns at reception data setup time t su;dat mclk* 1 ? 20 ? ns at reception
mb95100a series 50 (continued) (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : refer to ? (2) source clock/machine clock? for mclk. *2 : ? m is cs4 bit and cs3 bit (bit 4 and bit 3) of clock control register (iccr) . ? n is cs2 bit to cs0 bit (bit 2 to bit 0) of clock control register (iccr) . ? actual timing of i 2 c is determined by m and n values set by the machine clock (mclk) and iccr [4 : 0]. ? standard-mode : m and n can be set at the range : 0.9 mh z < mclk (machine clock) < 10 mhz. setting of m and n determines the mach ine clock that can be used below. (m, n) = (1, 8) : 0.9 mhz < mclk 1 mhz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 mhz < mclk 2 mhz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 mhz < mclk 4 mhz (m, n) = (1, 98) : 0.9 mhz < mclk 10 mhz ? fast-mode : m and n can be set at the range : 3.3 mh z < mclk (machine clock) < 10 mhz. setting of m and n determines the ma chine clock that can be used below. (m, n) = (1, 8) : 3.3 mhz < mclk 4 mhz (m, n) = (1, 22) , (5, 4) : 3.3 mhz < mclk 8 mhz (m, n) = (6, 4) : 3.3 mhz < mclk 10 mhz parameter sym- bol i/o timing unit remarks min max sda scl (at wakeup function) t wake- up oscillation stabili- zation wait time + 2 mclk* 1 ? 20 ? ns
mb95100a series 51 5. a/d converter (1) a/d converter electrical characteristics (avcc = vcc = 1.8 v to 3.3 v [flash product], avcc = vcc = 1.8 v to 3.6 v [mask product], avss = vss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max resolution ? ?? 10 bit total error ? 3.0 ? + 3.0 lsb linearity error ? 2.5 ? + 2.5 lsb differential linear error ? 1.9 ? + 1.9 lsb zero transition voltage v ot avss ? 1.5 lsb avss + 0.5 lsb avss + 2.5 lsb v flash product : 2.7 v avcc 3.3 v mask product : 2.7 v avcc 3.6 v avss ? 0.5 lsb avss + 1.5 lsb avss + 3.5 lsb v 1.8 v avcc < 2.7 v full-scale transition voltage v fst avr ? 3.5 lsb avr ? 1.5 lsb avr + 0.5 lsb v flash product : 2.7 v avcc 3.3 v mask product : 2.7 v avcc 3.6 v avr ? 2.5 lsb avr ? 0.5 lsb avr + 1.5 lsb v 1.8 v avcc < 2.7 v compare time ? 0.6 ? 16,500 s flash product : 2.7 v avcc 3.3 v mask product : 2.7 v avcc 3.6 v 20 ? 16,500 s 1.8 v avcc < 2.7 v sampling time ? 0.4 ? s flash product : 2.7 v avcc 3.3 v mask product : 2.7 v avcc 3.6 v external impedance < at 1.8 k ? 30 ? s 1.8 v avcc < 2.7 v external impedance < at 14.8 k ? analog input current i ain ? 0.3 ? 0.3 a analog input voltage range v ain avss ? avr v reference voltage ? avss + 1.8 ? avcc v avr pin reference voltage supply current i r ? 400 600 a avr pin, during a/d operation i rh ?? 5 a avr pin, at stop mode
mb95100a series 52 (2) notes on using a/d converter ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the exte rnal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. to satisfy the a/d conversion precision standard, co nsider the relationship between the external impedance and minimum sampling time and either adjust the resi stor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. if the sampling time cannot be suffici ent, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |avr - av ss | becomes smaller, values of relative errors grow larger. r c analog input pin note : the values are reference values. ? analog input circuit model rc 2.7 v avcc 3.6 v 1.7 k ? (max) 14.5 pf (max) 1.8 v avcc < 2.7 v 84 k ? (max) 25.2 pf (max) comparator during sampling : on 0 5 10 15 20 25 30 35 4 0 0 10 20 30 40 50 60 70 80 90 1 00 0123 4 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] av cc 1.8 v av cc 2.7 v av cc 2.7 v ? the relationship between external impedance and minimum sampling time
mb95100a series 53 (3) definition of a/d converter terms resolution the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, anal og voltage can be divided into 2 10 = 1024. linearity error (unit : lsb) the deviation between the value along a straight line connecting the zero tran sition point (?00 0000 0000? ?00 0000 0001?) of a device and the full-scale transition point (?11 1111 1111? ?11 1111 1110?) compared with the actual conversion values obtained. differential linear error (unit : lsb) deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. total error (unit: lsb) difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. (continued) v fst 1.5 lsb 3 ff h 3 fe h 3 fd h 004 h 003 h 002 h 001 h 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 1 lsb 0.5 lsb v ot av ss avr av ss v nt av r {1 lsb ( n ? 1 ) + 0.5 lsb} 1 lsb = avr ? avss 1024 (v) total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb ideal i/o characteristics total error digital output analog input analog input digital output [lsb] actual conversion characteristic actual conversion characteristic ideal characteristics v nt : a voltage at which digital out put transits from (n - 1) to n. =
mb95100a series 54 (continued) av ss avr av ss avr av ss av r v nt av ss avr 001 h 002 h 003 h 004 h 3fc h 3fd h 3fe h 3ff h 001 h 002 h 003 h 004 h 3 fd h 3 fe h 3ff h n - 2 n - 1 n n + 1 {1 lsb n + v ot } v nt v ( n + 1 ) t full-scale transition error digital output actual conversion characteristic actual conversion characteristic ideal characteristics analog input v fst (measurement value) zero transition error digital output actual conversion characteristic actual conversion characteristic analog input v ot (measurement value) ? 1 differential linear error in digital output n v (n + 1) t ? v nt 1 lsb linear error in digital output n v nt ? {1 lsb n + v ot } 1 lsb linearity error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics differential linear error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics v fst (measurement value) v ot (measurement value) v nt : a voltage at which digital outp ut transits from (n - 1) to n. v ot (ideal value) = avss + 0.5 lsb [v] v fst (ideal value) = avr ? 1.5 lsb [v] ideal characteristics = =
mb95100a series 55 6. flash memory program/erase characteristics *1 : t a = + 25 c, v cc = 3.0 v, 10000 cycles *2 : t a = + 85 c, v cc = 2.7 v, 10000 cycles *3 : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . parameter value unit remarks min typ max sector erase time (4 kb sector) ? 0.2* 1 3* 2 s excludes 00 h programming prior erasure. sector erase time (16 kb sector) ? 0.5* 1 12* 2 s excludes 00 h programming prior erasure. byte programming time ? 32 3600 s excludes system-level overhead. erase/program cycle 10,000 ?? cycle power supply voltage at erase/ program 2.7 ? 3.3 v flash data retension time 20* 3 ?? year average t a = +85 c
mb95100a series 56 mask option ordering information no. part number MB95107A mb95f108as mb95f108aw mb95fv100a-101 specifying procedure specify when ordering mask setting disabled setting disabled setting disabled 1 clock mode select ? single-system clock mode ? dual-system clock mode selectable single-system clock mode dual-system clock mode changing by the switch on mcu board 2 selection of oscillation stabilization wait time ? selectable the initial value of main clock oscillation stabili- zation wait time selectable 1 : (2 2 -2) /f ch 2 : (2 12 -2) /f ch 3 : (2 13 -2) /f ch 4 : (2 14 -2) /f ch fixed to oscilla- tion stabilization wait time of (2 14 -2) /f ch fixed to oscilla- tion stabilization wait time of (2 14 -2) /f ch fixed to oscillation stabilization wait time of (2 14 -2) /f ch part number package remarks MB95107Apfv mb95f108aspfv mb95f108awpfv 64-pin plastic lqfp (fpt-64p-m03) MB95107Apfm mb95f108aspfm mb95f108awpfm 64-pin plastic lqfp (fpt-64p-m09) mb2146-301 (mb95fv100a-101pbt) mcu board 224-pin plastic pfbga (bga-224p-m08) ()
mb95100a series 57 package dimensions (continued) 64-pin plastic lqfp (fpt-64p-m03) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins th ickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches). note: the values in parentheses are reference values. lead no. details of "a" part 0.25(.010) (stand off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.008) 0.500.20 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ? ~8 ? "a" 0.08(.003) (.006.002) 0.1450.055 0.08(.003) m (.008.002) 0.200.05 0.50(.020) 12.000.20(.472.008)sq 10.000.10(.394.004)sq index 49 64 33 48 17 32 16 1 2003 fujitsu limited f64009s-c-5-8 c (mounting height) *
mb95100a series 58 (continued) 64-pin plastic lqfp (fpt-64p-m09) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches). note: the values in parentheses are reference values. c 2003 fujitsu limited f64018s-c-3-5 0.65(.026) 0.10(.004) 116 17 32 49 64 33 48 12.000.10(.472.004)sq 14.000.20(.551.008)sq index 0.320.05 (.013.002) m 0.13(.005) 0.1450.055 (.0057.0022) "a" .059 ?.004 +.008 ?0.10 +0.20 1.50 0~8 ? 0.25(.010) (mounting height) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) details of "a" part (stand off) 0.10(.004) *
mb95100a series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0502 ? 2005 fujitsu limited printed in japan

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